1. Field of the Invention
The present invention is related to integrated circuits, and, in particular, is related to the packaging of integrated circuits so that a large quantity of integrated circuits can be physically located on the surface of a printed circuit board, or the like.
2. Description of the Related Art
The continuing advances in electronics technology, and in particular the technology related to integrated circuits, provide a steady improvement in the cost and performance of electronic circuits, particularly in the digital electronics and computer related fields. The complexity of integrated circuits has increased substantially in the years since such circuits were first developed and it is not unusual for a single integrated circuit to include all the circuit elements previously provided by a relatively large number of integrated circuits only a few years ago. Furthermore, the operational speeds of integrated circuits are also being improved both by using different technologies and by using smaller gates and shorter interconnections between gates to reduce propagation times.
Notwithstanding the increases in complexities and speeds of the integrated circuits, there continues to be a need to interconnect a large number of integrated circuits together to provide a complete system. For example, an exemplary computer system includes one or more processing elements (e.g., microprocessors), a plurality of memory circuits, device controller circuits, and input and output buffer circuits. These circuits are typically packaged in carriers, such as dual-in-line packages, flat packages, ceramic chip carriers, or the like. The carriers are typically interconnected on a printed circuit board, or the like. Although the speeds and circuit densities of the integrated circuits have increased substantially, much of the improvement is given up when conventional circuit packages on conventional planar circuit boards are used. The space required for the package material and the space required for the interconnection wiring between the integrated circuit carriers occupies a substantial portion of the board space. In addition, delays in the propagation of signals through the lengths of the interconnection wiring can be a significant portion of the signal propagation time. Thus, there are many disadvantages to the conventional combination of integrated circuit packages and printed circuit boards.
The foregoing problems have been recognized in some applications and attempts have been made to increase the packing density of integrated circuit elements. For example, there are hybrid circuit packages that include at least two integrated circuits in the same chip carrier. This technique continues to utilize the concept of mounting the integrated circuit dies in the same plane.
Other techniques have been developed wherein the integrated circuits are stacked vertically (i.e., normal to the plane of the active surfaces of the integrated circuit dies). For example, U.S. Pat. No. 4,398,235 illustrates the vertical stacking of dual-in-line packages. U.S. Pat. No. 4,288,891 illustrates a system of two integrated circuit dies in a double-cavity chip carrier that requires an interposed interconnection layer between the dies. U.S. Pat. No. 4,525,921 illustrates a system for packaging integrated circuit dies in the same package wherein the die is modified by etching a portion of the die to expose a portion of the metallization layer of the die. U.S. Pat. No. 3,999,105 illustrates a package for stacking semiconductor wafers.
A need continues to exist for a system of packaging a plurality of integrated circuits in a single package to achieve high packing density and using a minimum of printed circuit board space.